This invention relates to computer memories and more particularly to a DRAM memory subsystem capable of minimum wait state accessing by a high performance device outputting a series of row and column addresses for data to be accessed comprising, a DRAM comprised of rows and columns and operable in a static column mode in response to address requests asserted at RAS and CAS inputs thereof; and, access optimization logic means operably connected for receiving a first row and column address as output by the device, for asserting the first row and column address at the RAS and CAS inputs, for receiving a second row and column address as output by the device, for changing the column address being asserted at the CAS input to correspond to the second column address, for checking the second row address against the first row address, and for reasserting the second row and column address at the RAS and CAS inputs if the second row address is not the same as the first row address.
As depicted in FIGS. 1 and 2, it is known in the art to employ either a static RAM 10 or a dynamic RAM 12 to serve as a memory subsystem for a central processing unit (CPU) 14 which processes instructions contained in the RAM 10, 12 as well as reading from and writing to that memory. Commercial designs for instruction processors which are used in contemporary general purpose, high performance computing systems, however, require fast random access memory subsystems to sustain maximum performance. The instruction processor provides the memory subsystem with an address which identifies a location in the memory subsystem where data is stored. The memory subsystem must then provide quick access to the location so that the data stored in the location can be read from or written to by the processor. If the memory subsystem is incapable of accessing data at the rate which the processor requires for peak performance, the processor must wait for the memory access operation to complete. The time spent by the processor waiting for data directly decreases the performance of the computing system. This is a classic example of the old adage that a chain is only as strong as its weakest link. No matter how fast the computer processor may be, it can only operate as fast as it can access its data and instructions from memory.
The customary units for specifying the memory access time are clock cycles. The instruction processor executes instructions in one or more clock cycles. State-of-the-art designs such as so-called reduced instruction set computers (RISCs) strive to execute one instruction per clock cycle. Since each load and store instruction requires an access to the memory subsystem, these operations must also complete in one clock cycle if this design objective is to be achieved. For the same reasons, instructions from the memory subsystem must be delivered to the processor for execution at an average rate of one instruction per clock cycle.
A typical value for the clock period of a state-of-the-art design is 50 nanoseconds (ns). For example, the Motorola model 68030 instruction processor chip has a 50 ns clock cycle and the memory cycle time is less than two clock cycles or 100 ns. For the Motorola 68030 to operate without waiting for data, the Motorola company states, "When the MC68030 is operating at high clock frequency, a no-wait-state external memory subsystem will of necessity be composed of static RAMs." (MC68030 User's Manual, C. 1987, Sections 12-14). In other words, the Motorola company, like everyone else skilled in the art, is of the opinion that high performance instruction processors (and other high performance devices having to access memory subsystems) will not operate at their maximum performance capability (i.e. with no waiting for memory accesses) with dynamic random access memory (DRAM) as the memory.
The static RAM (SRAM) is a random access memory which provides access times from as low as 12 ns (but typically 45 ns) for state-of-the-art components. SRAM is built employing memory cells which each require six transistors. In contrast, DRAM is built of cells each requiring a single transistor; but, has a typical access time of 100 ns for state-of-the-art components with a cycle time of 200 ns. The cycle time indicates the maximum rate at which the DRAM can respond to memory access requests. A peculiarity of DRAM memory chips is that the devices require a significant "precharge" time when the row address is changed. Thus, as evidenced by the figures quoted above, DRAM cycle time is typically twice the time required to access the datum. In comparison, SRAM has a cycle time which is only slightly longer than its access time. The primary advantages of the DRAM over the SRAM are density and price; that is, more memory can be placed into the same space with DRAM because of the 6:1 reduction in the number of transistors for each cell of the memory. Obviously, the simpler design also results in a substantial cost reduction as well. Generally speaking, DRAM affords a 4:1 advantage in density and a 5:1 advantage in price. Such an advantage makes the use of DRAM over SRAM very desirable when possible. But, as we have seen, those skilled in the art have considered DRAM as unsuitable for use with high performance devices.
The DRAM market is highly competitive and the manufacturers of DRAM chips have produced novel variations on the customary organization of the DRAM to gain customer acceptance. One common variation is called "static column mode". Internally, as depicted in FIG. 3, a DRAM 12 is organized as a two-dimensional array of rows 16 and columns 18. The memory address employed for reading and writing the DRAM 12 is partitioned into a row address and a column address. With a static RAM 10, the row and column addresses are input in parallel as depicted in FIG. 4. As depicted in FIG. 5, however, in the dynamic RAM 12 the row address is first strobed into the memory device followed by the column address. As depicted in FIG. 6, this is accomplished by the CPU 14 providing its request to address forming logic 20 which, in turn, transmits the address information over the unmultiplexed address line or address bus 22 to a multiplexer (MUX) 24. The MUX 24 transmits the row address and the column address to the DRAM 12. To access another memory location requires both strobes to be removed for a preset time period and then be reapplied in the same sequence, as depicted in FIG. 7. For static column mode operation, the first step remains the same; once the row address has been strobed in, however, any data within the column can be randomly accessed without changing the row and column strobes. The net effect is that any data within the column, called a "page", can be accessed as if the data were stored in SRAM.
The principal application for static column mode operation in DRAMs is to provide copying of data from one page to another page, i.e. with the row address remaining the same, only the column address need be changed. This mode is particularly useful for disk controllers and other peripherals which employ direct memory to memory copy operations. The access and cycle times for DRAM operating in static column mode are competitive with purely static RAM parts.
Wherefore, it is the main object of the present invention to provide an interface and method of operation which will permit DRAM to be employed in place of SRAM with high performance devices without high risk of imposing wait conditions on the devices thereby.
It is another object of the present invention to employ the static column mode of operation in DRAMs in a manner which will provide high performance devices with a high density, low cost memory subsystem having a statistically low probability of requiring the DRAM to change pages.
Other objects and benefits of the present invention will be recognized from the description which follows hereinafter when taken in conjunction with the drawing figures which accompany it.